1. Field of the Invention
This invention relates to data processing systems, and more particularly to an address translator for an associative memory system of a data processing system.
2. Description of the Prior Art
The associative memory system is used to increase the amount of memory available to the user beyond that which is actually present in the main memory of the system. Conventionally, a central processing unit (CPU) includes a dynamic address translator (DAT) to translate automatically a user associative memory address into an actual memory address of the data processing system employing the associative memory system.
FIG. 1 illustrates a data processing system of the prior art. The data processing system includes the central processing unit (CPU) 11, an input/output channel (I/O channel) 10 and a main memory (MM) 14. A page table 15 is stored in a portion of the main memory 14 to maintain the relationship between the associative address and the actual address. The address relationship is usually divided into two tables, one of which is called a segment table and the other is called the page table. In this instance, the two tables combined will be referred to as the page table. The CPU 11 has a dynamic address translator (DAT) 12 to translate the associative address into the actual address in referring to the page table 15. In general, the DAT 12 has a hardware portion called a translation look aside buffer (TLB) 13 for improving the speed of the address translation by storing a recently accessed portion of the page table 15 therein. This associative addressing system and the hardware thereof is well known to those skilled in the art, and though they are not explained here, for instance, they are explained in the manual titled "A guide to the IBM 4341 Processor Section 15" (GC20-1877) published by the IBM corporation.
The architecture of the prior art systems reduced hardware costs somewhat and improved the speed of the address translation as was then possible, with the then available semiconductor elements. However, recently new semiconductor memory elements have been developed and it is possible to obtain a much less expensive memory element with both a larger memory capacity and a much faster memory access time. In view of these recent developments in hardware technology, the prior art address translation systems and related hardware configuration no longer provide the most efficient operation.
Recently disclosed in my related copending U.S. patent application Ser. No. 305516, 10-5-81, now abandoned, corresponding to Japanese patent application Ser. No. 55-137575 is a data processing system that enables the user to use the main memory effectively with their user program by a system of address translation utilizing the benefits of recent developments in semiconductor technology. In the address translation of the prior art devices, the operating system (OS) can be used to design and revise the page table with general instructions, because the page table is stored in the main memory. However, the page table in the present invention is not included in the main memory which up until now made it impossible to address the page table with general instructions. The prior art technology currently uses the operating system (OS) to perform paging by relating a total group of pages to each other in order to improve efficiency. It is important to further improve efficiency such that the OS performs the total paging for a plurality of pages, without storing the page table in the main memory.